The 37h International Symposium on Power Semiconductor Devices and ICs

Date: June 1-5, 2025 _ Venue: Kumamoto-Jo Hall, Kumamoto, Japan
KUMAMON

kumamoto image ISPSD2025

ABSTRACT & BIOGRAPHY

Technology for p-GaN gate High-voltage Gallium Nitride Transistors

Mr. Yasuhiro Uemoto, Infineon Technologies, Japan

Abstract:

GaN power devices are basically normally on devices that take advantage of the superior material properties of 2DEG and high mobility due to the AlGaN/GaN heterostructure. This is a great gift from the nature. However, in actual use, normally off devices are strongly desired, and as a result of the challenges by many researchers, normally off structures with p-GaN gate become the mainstream in the market. In recent years, GaN has encountered chargers in the consumer market as a killer application, and the market has begun to expand. However, in the near future, in addition to the consumer market, there is no doubt that markets requiring more reliable devices, such as industrial and automotive, will expand drastically. This session will go back to the basics to explain the benefits and technologies of GaN power devices. E-mode GaN and d-mode GaN technologies will be outlined as well as a comparison of p-GaN gates in GIT and Schottky structures. In addition, Dyn Rdson behavior related to C in GaN buffers will be presented.

Mr. Yasuhiro Uemoto

Biography:

Yasuhiro Uemoto received the B.S. and M.S. degrees in Electronics from Kyoto University, Kyoto, Japan in 1985 and 1987, respectively. In 1987, he joined Semiconductor Devices Research Center of Panasonic corporation (former Matsushita Electric Industrial Co. Ltd). Since then, he has been engaged in the research and development and mass production of poly-Si TFT ICs, high-density SRAMs, FeRAMs, and high voltage GaN devices. He is one of the inventors of GIT (Gate Injection Transistor) and has been actively involved in the development of normally-off and collapse suppression of GaN devices. He transferred Panasonic's GIT technology to Infineon. He is currently in charge of the research and development of high-voltage GaN devices and their next-generation development at Infineon as a senior principal engineer since 2022. He is the Category chair of GaN session of ISPSD 2025 and served as a member of Organizing Committee of ISPSD 2010 and a member of Technical Program Committee of ISPSD for GaN session 2009, 2014-2018 and 2024-2025.

IMPORTANT DATES

Submission deadline: February 14, 2025
Author Notification: March 24, 2025
Registration starts: January 2025
February 2025

Sponsored by

IEEJ
The Institute of Electrical
Engineers of Japan

Technically Co-sponsored by

IEEE
EDS
PELS
IAS

This conference is supported by JSPS KAKENHI Grant Number 24HP0701.

Organizer

The Institute of Electrical Engineers of Japan

Secretariat

ISPSD 2025 Secretariat
c/o Convention Linkage, Inc.
2-17 Sakuramachi, Chuo-ku, Kumamoto City 860-0805, JAPAN
Phone: +81-96-288-0882
Fax: +81-96-288-0883
Email: ISPSD2025@c-linkage.co.jp