The 37h International Symposium on Power Semiconductor Devices and ICs

Date: June 1-5, 2025 _ Venue: Kumamoto-Jo Hall, Kumamoto, Japan
KUMAMON

kumamoto image ISPSD2025

SHORT COURSE

SHORT COURSE PROGRAM

Date: June 1 (Sunday) 8:30-16:30
Short Course Chair: Dr. Tatsuya Nishiwaki, Toshiba Electronic Devices & Storage, Japan

08:40 - 9:30

200mm SiC Substrate development and 300mm SiC opportunities & challenges

Dr. Chao Gao, SICC, China

09:30 - 10:20

Technology for p-GaN gate High-voltage Gallium Nitride Transistors

Mr. Yasuhiro Uemoto, Infineon Technologies, Japan

10:50 - 11:40

Overview of Silicon Power Devices: History, Trends and Outlook

Prof. Wataru Saito, Kyushu University, Japan

11:40 - 12:30

Recent Requirements and Trends on Power IC Technology

Dr. Sang Gi Lee, DB Hitek, Korea

14:00 - 14:50

Power Electronics Design Automation Tools: Steps towards Realization

Dr. Tristan Evans, PE-Systems, Germany

14:50 - 15:40

AI-assisted Reliability Testing, Modeling, and Condition Monitoring for Power Semiconductor Modules

Prof. Huai Wang, Aalborg University, Denmark

15:40 - 16:30

Chip Embedded Power Package Technologies for AI and Vehicles

Mr. Yoshiaki Aizawa, AOI ELECTRONICS, Japan

IMPORTANT DATES

Submission deadline: February 14, 2025
Author Notification: March 24, 2025
Registration starts: January 2025
February 2025

Sponsored by

IEEJ
The Institute of Electrical
Engineers of Japan

Technically Co-sponsored by

IEEE
EDS
PELS
IAS

This conference is supported by JSPS KAKENHI Grant Number 24HP0701.

Organizer

The Institute of Electrical Engineers of Japan

Secretariat

ISPSD 2025 Secretariat
c/o Convention Linkage, Inc.
2-17 Sakuramachi, Chuo-ku, Kumamoto City 860-0805, JAPAN
Phone: +81-96-288-0882
Fax: +81-96-288-0883
Email: ISPSD2025@c-linkage.co.jp